1. Field of the Invention
This invention relates to the field of circuit simulation. In particular, the invention relates to a system and method of simulating a circuit by modifying a programmable logic device representation of that circuit. The modified representation is then used in a simulation of the circuit.
2. Description of Related Art
Programmable logic devices are a class of devices that allow a user to program a device to perform the function of a particular circuit. Examples of programmable logic devices are FPGAs (field programmable gate arrays) and FPLDs (field programmable logic devices).
In some cases, where the economies of scale warrant, a designer will want to target a circuit design for a different implementation technology. That is, a designer will want to convert a circuit design to a technology (e.g., mask programmed integrated circuit technology) other than in a programmable logic device. A Mask Programmed Integrated Circuit (MPIC) version reduces the silicon area needed to implement the circuit design and is therefore less expensive. This conversion process may be to a simple mask programmed version of the PLD, or a totally different representation; but the user logic functionality is maintained. One example of such a process is described in U.S. Pat. No. 5,550,839 entitled, "Mask-Programmed Integrated Circuits Having Timing and Logic Compatibility to User-Configured Logic Arrays," assigned to the assignee of this application.
As part of the process of implementing the circuit design in the target technology, the designer verifies the target technology implementation's operation. The purpose of verifying the implementation's operation is to ensure that implementation's function is equivalent to the function of the programmable logic device's implementation. Ensuring the functionally equivalent operation of the target technology's implementation is exceptionally important. The designer wants to simply replace the programmable logic device with the new integrated circuit. For a straightforward replacement, the new integrated circuit must be a functional equivalent of the programmable logic device's implementation of the circuit design.
One method of verifying the target technology implementation uses simulation tools. A simulation tool simulates a circuit design in a given target technology implementation. For example, to simulate an implementation of a circuit design in an XC4000.TM. FPGA, available from Xilinx, Inc. of San Jose, Calif., the designer first captures the circuit design using a schematic capture tool such as the ViewDraw.TM. tool from ViewLogic, Inc. of Milpitas, Calif. The designer then compiles the circuit design into an LCA.TM. file (Logic Cell Array file) using the XACT Step.TM. tools, available from Xilinx, Inc. The LCA file describes a physical netlist description of a programmed FPGA that implements the circuit design. The LCA file includes timing characteristics that can be used to simulate the circuit design as implemented in the PLD. The designer then converts the LCA file to an XNF.TM. file (Xilinx Netlist Format file) using the LCA2XNF.TM. tool, available from Xilinx, Inc. The XNF file provides a human readable high level design language description of the netlist defined in the LCA file. The XNF file also includes the timing characteristics from the LCA file. The XNF file can now be used as input to a simulator such as the VSS.TM. simulator, available from Synopsys, Inc. That is, the XNF file represents a simulation model for the FPGA implementation of the circuit design. The resulting FPGA simulation model is used by the designer to test the FPGA's implementation of the circuit design and verify the functionality of the circuit design.
To simulate the same circuit design implemented in an MPIC, the designer first converts the PLD implementation of the circuit design into an MPIC model. The conversion results in a netlist description of the circuit design implemented in the MPIC.
From the netlist description, the designer can partially simulate the MPIC implementation of the circuit design. However, because the netlist has not been placed and routed, it is difficult to guarantee the functional relationships and the timing relationships between the MPIC and the FPGA implementations of the circuit design. To completely simulate the MPIC implementation of the circuit design, the designer first places and routes the netlist. The timing information from the place and route is then used to back annotate the netlist. The back annotated netlist can then be used to simulate the MPIC implementation.
Importantly, generating the MPIC netlist is time consuming. Further, generating the placed and routed MPIC netlist requires substantially more time. Thus, it is desirable to have a faster method of generating a model for simulating the MPIC. It is also desirable to not have to perform the time consuming place and route and back annotation steps to generate a simulation model for the MPIC implementation.